Projects tagged physical-design: Physical-design methodologies for ASIC, SoC, and FPGA layout—floorplanning, placement, routing, and timing-closure solutions
Explore projects filtered by the tags > physical-design to discover hardware-aware layout and optimization workflows for ASICs, SoCs, and FPGAs; this curated list highlights long-tail topics like physical design optimization for tapeout, RTL-to-GDSII integration, floorplanning and placement strategies, routing and congestion management, static timing analysis (STA), and power-integrity techniques. Each project entry includes actionable insights, implementation notes, repositories, benchmarks, and integration patterns so you can evaluate PPA trade-offs and reproduce results. Use the filtering UI to narrow by sub-tags (floorplanning, placement, routing, STA, signoff) and compare case studies, open-source tools, and vendor-supported flows to accelerate chip development. Browse and filter these projects now to find practical solutions, implementation examples, and partners that match your architecture and performance targets.
